Recent questions tagged hdl

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hdl - What is the difference between reg and wire in a verilog module

What is the difference between a reg and a wire? When are we supposed to use reg and when are we supposed ... able to find a clear explanation. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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hdl - How does adding 1'b1 to 8 bit reg work in Verilog?

I am absolute beginner in Verilog and I am wondering how does the addition statement work in this piece of program. reg ... /how-does-adding-1b1-to-8-bit-reg-work-in-verilog...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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hdl - What is the difference between reg and wire in a verilog module

What is the difference between a reg and a wire? When are we supposed to use reg and when are we supposed to ... /what-is-the-difference-between-reg-and-wire-in-a-verilog-module...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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hdl - Implementing a Repetition error correcting code in Verilog

I want to use an FPGA to implement an error correction code but I'm running into some issues. I started ... combinational logic, I would appreciate any help regarding this issue....

asked Jan 27, 2021 in Technique[技术] by 深蓝 (71.8m points)

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hdl - chip Mux4way16 not run ontil the end on ?HardwareSimulator (VHDL)

I'm tryng to build this chip: // This file is part of www.nand2tetris.org // and the book "The Elements of Computing Systems" ... [2]; OUT out[16]; PARTS: // Put your code here:...

asked Jan 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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