Recent questions tagged vhdl

0 votes

1.5k views

1 answer

vhdl - shift a std_logic_vector of n bit to right or left

I have a vector signal tmp : std_logic_vector(15 downto 0) I have to shift it to left or right of n bit. how can ... I didn't know how use it. See Question&Answers more detail:os...

asked Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

532 views

1 answer

vhdl - Using std_logic_vector with logical operators

I'm trying to use logical operators on an std_logic_vector signal and an std_logic signal, and get an ... com/questions/65929565/using-std-logic-vector-with-logical-operators...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

456 views

1 answer

vhdl - How to access implicit "=" function for an array type when it is overloaded in the same package?

I had a sudden thought. Is it possible to access the implicit "=" function for an array type when an overload ... implicit-function-for-an-array-type-when-it-is-overloaded-in-t...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

634 views

1 answer

vhdl - clk'event vs rising_edge()

I had always used this for detecting a rising edge: if (clk'event and clk='1') then but this can ... from:https://stackoverflow.com/questions/15205202/clkevent-vs-rising-edge...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

884 views

1 answer

vhdl - clk'event vs rising_edge()

I had always used this for detecting a rising edge: if (clk'event and clk='1') then but this can ... from:https://stackoverflow.com/questions/15205202/clkevent-vs-rising-edge...

asked Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

556 views

1 answer

vhdl - Reset of FIFO (Asynchronous or Synchronous) obtained during instantiating FIFO from IP core of XILINX ISE is active low or active high?

I am using FIFO from IP core generator, which is BRAM-based operating at a common clock for reading ... -of-fifo-asynchronous-or-synchronous-obtained-during-instantiating-fifo-f...

asked Oct 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

605 views

1 answer

vhdl - Error: Signal parameter requires signal expression on function call

Short question: I've written a function that takes a signal integer as parameter. The compiler throws the ... /error-signal-parameter-requires-signal-expression-on-function-call...

asked Oct 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

1.1k views

1 answer

vhdl - "GT0 is not compiled in xil_defaultlib" and "gt is not declared"

this is my first time working in VHDL, and I was wondering why I am getting an error of "gt1 is not compiled in ... /gt0-is-not-compiled-in-xil-defaultlib-and-gt-is-not-declared...

asked Oct 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

0 votes

567 views

1 answer

vhdl - 读/写具有时钟上升沿和读/写使能信号的向量数组(Read/writing to array of vectors with clock rising edge and read/write enable signal)