This looks like one more simple, useful, logical thing that Make should be able to do, but isn't.
Here is a workaround. If the clean
rule is set up correctly, Make can execute it whenever the makefile has been altered, using an empty dummy
file as a marker.
-include dummy
dummy: Makefile
@touch $@
@$(MAKE) -s clean
This will work for most targets, that is targets that are actual files and that are removed by clean, and any targets that depend on them. Side-effect targets and some PHONY
targets will slip through the net.
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