arm - What is PDE cache?

Question

I have the following specifications of an ARM based SoC:

• L1 Data cache = 32 KB, 64 B/line, 2-WAY, LRU
• L2 Cache = 1 MB, 64 B/line, 16-WAY
• L1 Data TLB (for loads): 32 entries, fully associative
• L2 Data TLB: 512 entries, 4-WAY
• PDE Cache: 16 entries (one entry per 1 MB of virtual space)

And I wonder what is the PDE cache? I guess it's something similar to TLB, but I'm not sure.

Answer
It seems that PDE (Page Directory Entry) is Intermediate table walk cache which indeed can be implemented separately from TLB.

The Cortex-A15 MPCore processor implements dedicated caches that store intermediate levels of translation table entries as part of a table walk.

Answer 1

A PDE ("Page Directory Entry") is x86 architecture terminology for a top level^* page table entry - the equivalent of a "first-level descriptor" in ARM VMSA terms.

Assuming this is the source of the data in the question, it's presumably referring to Cortex-A15's "intermediate table walk cache", which is not entirely appropriate since that can actually cache any level of translation.

_{* in IA-32 at least - 64-bit mode has levels above this}