Implementing Sequential Circuit in Verilog

Question

I'm trying to implement the following Sequential Circuit in Verilog (Modelsim 10.4a)

Here's the code I'm using

seq_circuit1.v

module seq_circuit1(x, clk, Q0, Q1);
 input x, clk;
 output Q0, Q1;
 reg J0,K0,J1,K1;
always @(negedge clk)
begin
 //Blocking and Non Blocking both will work
 J0 = Q1 & ~x;
 K0 = Q1 & x;
 J1 = x;
 K1 = (Q0 & x) || (~Q0 & ~x);
 jkfflop JKff0 (J0,K0,Q0);
 jkfflop JKff1 (J1,K1,Q1);
end
endmodule

jkfflop.v

module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;
 if(J==0 & K==1)
  begin
   assign Q = 0;
  end
 else if(J==1 & K==0)
  begin
   assign Q = 1;
  end
 else if(J==1 & K==1)
  begin
   assign Q = ~Q;
  end
endmodule

I'm getting some errors and I'm unable to figure out why. Can anybody tell me where did I do it wrong..

Answer 1

seq_circuit1

• You can't instantiate submodules (your FFs) inside an always block. Move them outside, either before or after.
• Your instantiations for jkfflop are missing the clk input signal.
• based on your diagram, your inputs to the FFs should be combinational logic, not sequential, and should therefore use an always @(*) block, not a clocked one.

jkfflop

• if statements in verilog are only valid inside a generate, always or inital block. Since this is a FF, you'll want an always @(posedge clk) or always @(negedge clk)
• If using an always block, replace the assign statements with non-blocking assignments (<=). We use NBA's here instead of a blocking assignments (=), as it's an edge-triggered block.
• If assigning a value to Q inside an always block, change output Q to output reg Q