verilog - $fgetc SystemVerilog function doesn't read from stdin

Question

In the following testbench

module for_loop;

    int c; 
  
  initial begin
    $display("Write Here!");
    c = $fgetc('h8000_0000);
    $display(c);
  end 
endmodule

I get the output:

Write Here!
ERROR: File descriptor (-2147483648) passed to $fgetc in file C:/Users/Halib/XilinxVivadoWorkspace/project_7/project_7.srcs/sim_1/new/tb_q2.sv at line 8 is not valid.
         -1

Someone can help?

I'm using Vivado 2019.1

question from:https://stackoverflow.com/questions/65841430/fgetc-systemverilog-function-doesnt-read-from-stdin

Answer 1

Waitting for answers